The present invention concerns an accurate timing model for logic simulation of integrated circuits. The timing model reflects the timing delays caused by input ramp and output load of circuitry.
When designing an integrated circuit, it is generally desirable to simulate the functioning of logic circuitry within the integrated circuit. In order to accurately access the performance of the circuitry, it is additionally desirable that the logic simulation of logic include an accurate assessment of timing delays through the circuitry, at least in the critical paths.
In general, timing delays through circuitry are caused by propagation delays through and between logic cells which comprise the circuitry. The actual amount of propagation delay through and between logic cells is generally dependent on various capacitances within and between the logic cells, as well as the current available to charge or discharge the capacitances.
When developing a timing model, it is desirable to take into account the time delay introduced by charging the input capacitance of logic cells. This time delay is directly affected by the input current available to charge the input capacitance to the logic cell. This input current, in turn, is directly affected by the fan out of the output of the logic cell providing the input current.
In the prior art, timing delay caused by charging input capacitance was approximated as being directly proportional to the output fan out of the logic cell providing current for the input. However, this has proved to be an inaccurate modelling technique because propagation delay through the logic cell is additionally influenced by the shape of the voltage input ramp of the input signal to the logic cell. The effect of the shape of the voltage input ramp on the timing delay may be approximated by using general piecewise linear functions of the voltage input ramp and the output load. However, this approach does not easily lead to a practical characterization system. In order to obtain a fairly accurate timing model, a circuit simulation needs to be performed for every grid point of the function. A sufficient number of grid points need to selected to obtain the desired accuracy of the timing model. This can require numerous circuit simulations.